In a digital frame synchronizer, gen-lock circuits are used to generate trains of pulses for timing operation of the frame synchronizer in relation to an input video signal and a reference video signal respectively. The input gen-lock circuit, for example, generates pulses which are timed with reference to the horizontal sync edges of the input video signal. A problem may arise, however, in the event that the input video signal is noisy, since it may then contain spurious sync pulses, i.e., pulses which appear to the gen-lock circuit to the sync pulses but are not in fact valid sync pulses, and true sync pulses may be missing. This disturbs operation of the gen-lock circuit, to the extent that it may lose lock and may cause the frame synchronizer to go into a freeze mode.